This invention relates to a data pulse receiver arrangement of a type suitable for the acquisition of data pulses of the NRZ (nonreturn to zero) type which occur in a serial bit stream in a received information signal in which one level of the signal (say high) represents a binary value `1` and another level of the signal (say low) represents a binary value `0`, said arrangement including a data clock pulse generator which produces clock pulses for clocking the data pulses into the data pulse receiver arrangement, the period of a clock pulse cycle being equal to a data bit period. (A data pulse receiver arrangement of the above type is known, for instance, from Mullard Technical Information Article 54, dated August 1977).
The invention relates more particularly to a phase sensitive detector in, or for use with, such a data clock pulse generator for producing a control signal which is indicative of a phase discrepancy between the data pulses and the clock pulses and which can be used to correct the phase of the clock pulses generated to achieve the required phase relationship between the data pulses and the clock pulses.
Phase sensitive detectors which operate in digital fashion have already been used extensively for detecting the phase of a data pulse clock relative to a serial bit stream of data pulses, and for producing a control signal which is indicative of the phase discrepancy. In some forms of such phase sensitive detectors, it is known to use D-type flip-flop for detecting the relative timing of data pulses and clock pulses.
One example of this form of phase detector is described in U.S. Pat. No. 3,986,125, and another example is described in U.K. patent specification No. 1,445,725. In these known forms of phase sensitive detector, it is the practice for only one edge, usually the leading edge, of a received data pulse to be used for detecting the relative timing of data pulses and clock pulses. This practice is clearly evidenced in the two specific prior art examples mentioned above, in each of which examples, the clock input of the D-type flip-flop receives the data pulses and the D input receives the clock pulses.
Where a serial bit stream of data pulses is deemed to be "continuous" by virtue of the fact that a succession of its data pulses occur for a significant duration with interruption, a phase sensitive detective which operates only on one edge of the received data pulses is able nevertheless to perform sufficient phase detections to produce a control signal which indicates the phase discrepancy between data pulses and clock pulses with acceptable accuracy. Also, since the data pulses are "continuous" the control signal can be altered continually to indicate any drift from the required phase relationship.
However, situations can occur where data pulses of a serial bit stream are received in short bursts with relatively lone interruptions between successive bursts. In such a situation, a phase sensitive detector which operates only on one edge of the received data pulses may not be able to perform sufficient phase detections in response to a short burst of data pulses to produce a sufficiently accurate control signal for indicating phase discrepancy between the data pulses and the clock pulses.
In particular, such a situation occurs in a television transmission system of a character in which coded data pulses, representing alpha-numeric text or other message information, are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present. (United Kingdom patent specification No. 1 370 535 discloses a television transmission system of this character, an example of which is the BBC/IBA Teletext television transmission system).